1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
15:
16:
17:
18:
19:
20:
21:
22:
23:
24:
25:
26:
27:
28:
29:
30:
|
library ieee;
use ieee.std_logic_1164.all;
entity Baudratengenerator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC);
end Baudratengenerator;
architecture Behavioral of Baudratengenerator is
signal counter : integer := 0;
begin
P1: Process(clk, rst)
begin
if clk'event and clk = '1' then
if rst = '1' then
tick <= '0';
counter <= 0;
else
counter <= counter + 1;
if counter = 5 then
tick <= '1';
counter <= 0;
else
tick <= '0';
end if;
end if;
end if;
end Process;
end Behavioral; |