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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Toplevel_A is
port( CLK, RST : in std_logic;
A : out std_logic_vector(2 downto 0));
end entity;
architecture Behavioral of Toplevel_A is
signal sr : std_logic_vector(2 downto 0);
signal invert : std_logic;
begin
A <= sr;
invert <= not sr(0);
process(CLK,RST) begin
if RST = '1' then
sr <= "000";
elsif CLK'event and CLK = '1' then
sr <= invert & sr(2) & sr(1);
end if;
end process;
end architecture; |
