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entity Baudratengenerator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC);
end Baudratengenerator;
architecture Behavioral of Baudratengenerator is
signal counter : integer;
begin
P1: Process(clk, rst)
begin
if clk'event and clk = '1' then
if rst = '1' then
tick <= '0';
counter <= 0;
else
counter <= counter + 1;
if counter = 5208 then
tick <= '1';
counter <= 0;
else
tick <= '0';
end if;
end if;
end if;
end Process;
end Behavioral; |